COS/MOS parallel processor array
A.A. Alaspa, Andrew G. F. Dingwall · 1970
A report on an LSI, COS/MOS parallel processor array posessing functional capabilities of an arithmetic unit 4-bit slice, will be presented. High functional density was achieved using functional gating and transmission gating to reduce device requirements. The data-transfer rate for a 4-bit add is 1.4 μs including instruction decode.