Multi-bit Error Correction Technique for NTC based Network on Chip
2018
To fulfill the communication requirements of System on Chip(SoC) the latest promising solution isNetwork on Chip(NoC).It is packet switching based technology used in multicore SoC.Unreliability is one of the significant challenge faced by NoC architectures due to technology limitations.Near-Threshold Computing can also be introduced in NoC, but it comes with transient faults.Through error control techniques NoC can achieve reliability as well as energy efficiency.In this paper duplicate consecutive sextuple error correction technique is proposed to handle multiple errors, and its results are assessed in NoC.It is proved that the proposed error correction scheme is better in error correction capability than previous error correction schemes to make NoC architectures reliable and energy efficient, with lower latency.