Quasi-Universal VLSI Multiplier with Signed Digit Arithmetic
Simon Vassiliadis, Eric M. Schwarz, M. Putrino · 2005
An algorithm is proposed for the design of a quasi-universal multiplier, i.e. one that can multiply two binary numbers and yield, upon instruction specification, the product in sign magnitude, two's complement or one's complement notation. The partial product matrix is created with direct multiplication and then reduced with signed digit additions.