Sequential VHDL
Andrew Rushton · 2011
Very-high speed integrated circuits programme (VHSIC) hardware description language (VHDL) covers two programming domains: concurrent domain and sequential domain. This chapter discusses sequential domain, which is analogous to the domain of conventional programming languages. Signals are the interface between VHDL’s concurrent domain and the sequential domain within the process. Variables are used to store intermediate values within a process. They only exist within sequential VHDL and cannot be declared or used directly in an architecture. The if statement is the sequential equivalent of the conditional signal assignment, although they are not exactly equivalent. The technique used by synthesisers to convert asynchronous feedback to latches is known as latch inference. A loop is a mechanism for repeating a section of VHDL code, for example to process every element in an array in the same way. The chapter illustrates an example to design a BCD to 7-segment decoder with zero blanking. Controlled Vocabulary Terms hardware description languages; programming languages; very high speed integrated circuits