Clock Network Design: Basics
Chris Chong-Nuen Chu, Min Pan · Auerbach Publications eBooks · 2008
This chapter discusses some basic issues in clock network design. It introduces the metrics used in designing clock networks. The chapter describes algorithms to generate clock networks with tree structures and nontree structures. It examines the clock skew scheduling technique, which makes use of intentional clock skew to optimize performance. The chapter presents clock network design techniques that focus on handling variability. Clock skew refers to the spatial variation in the arrival time of a clock transition. Transition times also need to be substantially less than the clock period to allow the clock to achieve a rail-to-rail transition, to provide adequate noise immunity. Phase delay is defined as the maximum delay from the clock generator to any clock terminal. The clock distribution and generation circuitry is known to consume up to 40 percent and 36 percent of the total power budget of high-performance and embedded microprocessors, respectively.