A 2.5 GFLOPS 6.5 million polygons per second 4-way VLIW geometry processor with SIMD instructions and a software bypass mechanism
N. Higaki, H. Kubosawa, S. Ando, H. Takahashi, Y. Asada, H. Anbutsu, T. Sato, M. Sakate, Atsuhiro Suga, M. Kimura, H. Miyake, H. Okano, A. Asato, Y. Kimura, H. Nakayama, M. Kimoto, K. Hirochi, H. Saito, N. Kaido, Y. Nakagawa · 2003
A 4-way VLIW geometry processor runs at 312 MHz and contains a PCI/AGP bus bridge in a three-layer-metal CMOS process with 0.21 /spl mu/m design rules at 2.5 V. It features: (1) VLIW and SIMD instruction sets, (2) a software bypass mechanism, (3) special condition-code registers and branch condition generator for clipping, and (4) automatic clock delay tuning. The result is performance of 2.5 GFLOPS and 6.5 Mpolygons/s in a 3D geometry processor. This chip can be added to conventional graphics systems without requiring additional LSIs.