Efficient analog circuit synthesis with simultaneous yield and robustness optimization
G. Debyser, Georges E. Gielen · 2002
Article Efficient analog circuit synthesis with simultaneous yield and robustness optimization Share on Authors: Geert Debyser Katholieke Universiteit Leuven, Belgium Katholieke Universiteit Leuven, BelgiumView Profile , Georges Gielen Katholieke Universiteit Leuven, Belgium Katholieke Universiteit Leuven, BelgiumView Profile Authors Info & Claims ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided designNovember 1998 Pages 308–311https://doi.org/10.1145/288548.288630Published:01 November 1998 19citation251DownloadsMetricsTotal Citations19Total Downloads251Last 12 Months6Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access