Clock Subsystem
Vojin G. Oklobdzija · 2009
This chapter contains sections titled:Clock Distribution Networks in VLSI Circuits and SystemsClock System DesignClocking Schemes for High-Speed Digital SystemsClock Tree Synthesis Based on RC Delay BalancingHalf-Swing Clocking Scheme for 75% Power Saving in Clocking CircuitryA Reduced Clock-Swing Flip-Flop (RCSFF) for 63% Power ReductionA Unified Single-Phase Clocking Scheme for VLSI SystemsHigh-Speed CMOS Circuit TechniqueFlow-Through Latch and Edge-Triggered Flip-Flop Hybrid ElementsA 200-MHz 64-b Dual-Issue CMOS MicroprocessorA 300-MHz 64-b Quad-Issue CMOS RISC MicroprocessorA 600MHz Superscalar RISC Microprocessor with Out-of-Order ExecutionHigh-Performance Microprocessor Design