A high-density sea-of-gates architecture incorporating testability support
R.J.H. Koopman, H.G. Kerkhoff · 2003
A new CMOS sea-of-gates master array architecture is presented. In this architecture, not only are routing considerations taken into account, but also performance considerations. These routing and performance arguments have both been used to determine the transistor gate widths. In doing so a high-density sea-of-gates architecture has been designed with good routing and performance characteristics. Special hardware was incorporated in the architecture to support design for testability.>