Hardware Support for Efficient and Low-Power Data Sorting in Massive Data Application: The 3-D Sorting Method
Amin Norollah, Zahra Kazemi, Hakem Beitollahi, David Hély · IEEE Consumer Electronics Magazine · 2021
Sorting is an inseparable part of applications that process massive amounts of data. A hardware-designed sorter increases the performance at the cost of increasing the required resources, the issue that is limited in the field-programmable gate array (FPGA) chips. This article proposes a new ultralow-power three-dimensional hardware sorting architecture, the so-called ULP-Sorter, based on multidimensional sorting algorithm. The hardware resources and power consumption are significantly decreased in the ULP-Sorter architecture in comparison with previous state-of-the-art techniques. The simulation results show that ULP-Sorter reduces number of look-up tables and registers by 70% and 35.7%, respectively, in comparison to previous state-of-the-art techniques. ULP-Sorter reduces the FPGAs power consumption on average by 48.7% in comparison with previous state-of-the-art techniques. The results indicate that ULP-Sorter is a suitable architecture for edge computing devices with limited power and area constrains.