Improved Scheduling Algorithm for the IIR Filter design for Low power VLSI Applications
International Journal of Advanced Trends in Computer Science and Engineering · 2020
The behavioural synthesis of infinite impulse response (IIR) filter is a challenge when it comes to high speed VLSI design applications.Implementation in FPGA is quite impossible due to huge hardware requirements and it is a major obstacle to widespread acceptance.This paper presents the algorithm that makes design decisions to reduce power consumption.The operations are performed with proper scheduling techniques like as soon as possible (ASAP) and as late as possible (ALAP).The IIR filter is considered for this implementation so that it makes easier to identify the operations with successive clock cycles and resource utilization.The power consumption has been reduced by 15.27% with sampling rate from 10 MHz to 79 KHz.