Design of an application-specific PLD architecture
Jae‐Jin Lee, Gi-Yong Song · Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005. · 2005
This paper presents a new application-specific PLD architecture which adopts a bit-level super-systolic array for application-specific arithmetic operation such as MAC. The proposed design offers a significant alternative view on programmable logic device. The bit-level super-systolic array whose cells contain another systolic array is ideal for newly proposed PLD architecture in terms of area efficiency and clock speed as it limits the routing requirement in a PLD to local interconnections between logic units and to global interconnections between logic modules. The maximum clock cycle is limited only by one AND gate and one full adder.