Fast multiplier bit-product matrix reduction using bit-ordering and parity generaton
Ben C. Drerup, E.E. Swartzlander · 2003
The Wallace tree/Dadda fast multiplier consists of the three steps: (1) form a bit-product matrix; (2) reduce the bit-product matrix to two rows; and (3) sum the two rows. An approach for implementing the second step using bit-ordering and parity generation logic is described. This is very different from the Wallace/Dadda method, which uses full and half adders to reduce the bit-product matrix. The approach yields a multiplier that is faster than a Wallace-Dadda multiplier when multiplying small numbers. However, it also requires more gates to implement.>