A 160 MHz analog equalizer for magnetic disk read channels
S. Kiriaki, T.L. Viswanathan, G. Feygin, Robert Bogdan Staszewski, R. Pierson, B. Krenik, M. De Wit, K. Nagaraj · 2002
This prototype filter has five taps and operates at 160 MHz clock rate, dissipating 200 mW with 5 V supply. The filter occupies 1.35 mm/sup 2/ in BiCMOS with 0.8 /spl mu/m CMOS. It uses BiCMOS sample-and-hold (S/H) circuits to derive analog discrete-time samples, and CMOS time shared sign-sign LMS (SS-LMS) for coefficient adaptation. It improves on a previous analog signal shuffling structure by: (a) fast master S/H improves the dynamic performance and reduces effect of clock jitter on timing and gain recovery, (b) additional S/H amplifiers alleviate settling time requirements and reduce power, (c) time-interleaved LMS algorithm permits low-cost and low-power coefficient adaptation. DACs for taps and for dc offset cancellation are on-chip.