APPlaUSE: area and performance optimization in a unified placement and synthesis environment
O. Frank, T. Lengauer · 2002
We present a new methodology for high-level synthesis, which incorporates placement in an early phase of the synthesis process. This placement, prior to interconnect and storage allocation, allows for early and accurate estimates on area and net length. These cost factors are critical for the quality of the chip. The system has been implemented and extensive tests verify the estimates to be accurate.