The on-chip 3 MB subarray based 3rd level cache on an Itanium microprocessor
Don Weiss, J.J. Wuu, V. Chin · 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) · 2003
This 3 MB on-chip level-three cache employs subarray design style, and achieves 85% array efficiency. Characterized to operate up to 1.2 GHz, the cache allows a store and a load in every four core cycles, and provides a total bandwidth of 64 GB/s at 1.0 GHz.