A Scratchpad Memory with Advanced DMA for Data Transfer with Cache Assistance for Multi-bit Error Correction
Asapu Harika, Mr. A. Sai Kumar Goud, Mr. Pradeep Kumar Reddy · International Journal of Trend in Scientific Research and Development · 2018
Modern embedded processors includes memory (SPM) and cache memory in their architectures.SPM's are prone to soft errors like Single event upsets (SEUs) and Single event multiple upsets (SEMUs).For correcting soft errors, we use Error Correcting Codes (ECC) like singledouble-error detection(SEC-DED) and SEC double-adjacent error correction(SEC and parity duplication approach.These approaches are used only error correction for less number of corrections and thus increases speed.This paper proposes a duplication scheme, cache assisted duplicated SPM(CADS) to correct SEUs and SEMUs in data SPM lines detected by a low detecting code.This duplication approach does error detection in SPM which is faster than ECC providing multibit error correction.The extension is to include DMA with ring descriptors.The descriptor-based model provides the most flexibility in managing a system's DMA faster data transfers to or from Scratchpad memory.