An 8 ns random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D/sup 2/ RAM)
Y. Agata, Kenji Motomochi, Y. Kagenishi, Y. Fukushima, M. Shirahama, M. Kurumada, N. Kuroda, H. Sadakata, Kohtaro Hayashi, T. Yamada, K. Takahashi, T. Fujita · 2002
Recent multimedia applications and personal computers require enhanced memory systems. 3D-graphics and networking require faster random cycle and lower latency megabit-scale RAMs. However, the random cycle time of conventional DRAM is too slow and embedded SRAM area is too large to integrate high-density RAM on a chip. The fast random cycle low-latency embedded RAM macro reported here uses a dual-port interleaved DRAM architecture (D/sup 2/RAM). D/sup 2/RAM reduces random cycle time from 50 ns (20 MHz) of conventional DRAM to 8 ns (125 MHz) on a test chip with a 0.25 /spl mu/m embedded DRAM process. Key technologies are (1) interleaved open bitline operation with dual-port memory cell architecture, (2) two-stage pipelined circuit operation and (3) write before sensing (WBS).