Built-in intermediate voltage testing for CMOS circuits
Jing-Jou Tang, Kuen-Jong Lee, Bin-Da Liu · 2002
In this paper, we propose a new testing technique called built-in intermediate voltage testing for CMOS circuits. This technique provides a high quality test which cannot be achieved by conventional functional testing. Three novel circuit designs that can detect faults resulting in intermediate voltage values are presented. These designs can also be used to detect slow transition faults and the metastability of flip-flops. The detection speed, area overhead, circuit complexity, and the performance impact on the circuits under test are analyzed. The results validate the feasibility of these designs in CMOS testing.>