Raisin: Redundancy Analysis Algorithm Simulation
Rei-Fu Huang, Jen-Chieh Yeh, Jin-Fu Li, Cheng‐Wen Wu · IEEE Design & Test of Computers · 2007
To increase redundancy repair efficiency and thus final yield in embedded- memory cores, we propose Raisin, a redundancy analysis algorithm simulation tool that can calculate an RA algorithm's repair rate, yield, associated memory configuration, and redundancy structure. Raisin lets users easily assess and plan redundant elements and subsequently develop BIRA algorithms and circuits, which are essential for BISR of embedded memories.