A 1.71 M-transistor CMOS CPU chip with a testable cache architecture
Y. Saito, Yukihiko Shimazu, S. Kobayashi, T. Shimizu, M. Matsuo, A. Ohtsuka, K. Shirai, Hironori Murata, Y. Nishiwaki, I. Fujioka, Y. Nabeta, H. Kanamoto, Shoma Hiraoka, T. Suzuki, J. Hinata, Y. Shimotsuma · 1993
A CISC CPU chip for the business computer is described. It contains an integer unit (IU), a double-precision floating-point unit (FPU), an address generation unit (AGU), and a Harvard-style memory unit with cache. The memory includes two independent memory management units (DMMU and IMMU), an 8-kB D-cache, a 32-B store buffer (SB), and a bus-controller unit (BCU). An on-chip PLL (phase-locked loop) synchronizes external and internal clock edges with a skew of 1-ns. The chip is fabricated in a 0.8- mu m CMOS double-polysilicon double-metal technology. A 77- mu m/sup 2/ SRAM (static random-access memory) cell uses a high resistance load formed by the second polysilicon layer. The 16.3-mm*12.7-mm chip contains 1.71-M transistors. In 40-MHz operation, power consumption is 6 W with a 5-V supply. The design is verified by simulations at several levels, using a microsimulator for evaluating parallelism of a large horizontal microprogram.>