Reversible Fault‐Tolerant Decoder Circuit
Hafiz Md. Hasan Babu · 2020
Decoders are the collection of logic gates fixed up in a specific way such that, for an input combination, all outputs terms are low except one. These terms are the minterms. This chapter describes the design methodology of reversible fault-tolerant decoder circuit. It also describes two very popular reversible gates, namely, Feynman double gate and Fredkin gate. The chapter presents algorithm for designing the generalized decoder. It also describes several lower bounds on the number of constant inputs, garbage outputs, and quantum cost of the reversible fault-tolerant decoder. Transistor simulations of the decoder are shown using standard p-MOS 901 and n-MOS 902 models with delay of 0.030 ns and 0.12 µm channel length, which proved the functional correctness of the decoder circuits.