Design and Implementation of (72,64) Extended Multibit SEC-DAEC Codes in FPGA
Haindavi Police · International Journal for Research in Applied Science and Engineering Technology · 2019
Single error correction and Double-adjacent error correction (SEC-DAEC) codes speaks to a kind of error correction codes (ECCs) equipped for altering single and double-adjacent errors. These codes are important in applications where various adjacent errors may occur, for instance, space. ECC encoders and decoders have an even structure that makes it less demanding to place them into field-programmable gate arrays (FPGAs). This proposes techniques to develop the decoder of SEC-DAEC codes when executed in a FPGA, falling the advantage use when differentiated and the conventionalist use. This paper grows the bits and triple error cure in like manner achieved for that bits nearby SEC-DAEC codes. Keywords: Error Correction codes (ECC), Field Programmable Gate array (FPGA), Look up Table (LUTs), Single Error Correction and Double Adjacent Error Correction (SEC-DAEC).