Analysis of speed of a binary divider using a variable number of shifts per cycle
M. R. Patel · The Computer Journal · 1978
In a recent paper (1976), the analysis of a binary multiplier using a variable number of shifts per multiplication cycle was described. The method was based on a discrete time finite state system model. In this paper we continue the analysis for the more complex case of binary division. The results enable the optimum hardware configuration to be determined for a given cost.