A fully fledged TDC implemented in field-programmable-gate-arrays
Jinhong Wang, Shubin Liu, Qi Shen, Hao Li, Qi An · 2009
The motivation of this paper is to implement a fully fledged FPGA-based TDC in XILINX XC4VFX60 FPGAs, with the features of self-test, temperature variation compensation and trigger-matching. Self-test is performed with the statistical methods and gives the resolution of delay chain at its temperature and supplied voltage. The resolution changes with the environment temperature, and the corresponding value was recorded by self-test from 30~60degC for compensation. After compensation and INL calibration, the RMS of time measurement remains less than 30 ps per channel of the total six, and the resolution is about 50 ps. Trigger-matching is implemented using content addressable memory with the two parameters: trigger-latency and matching window programmable.