A Design Methodology of MIN-Based Network for MPPSoC on Reconfigurable Architecture
Y. Aydi, M. Baklouti, Ph. Marquet, M. Abid, J.L. Dekeyser · IGI Global eBooks · 2011
Massive parallel processing systems, particularly Single Instruction Multiple Data architectures, play a crucial role in the field of data intensive parallel applications. One of the primary goals in using these systems is their scalability and their linear increase in processing power by increasing the number of processing units. However, communication networks are the big challenging issue facing researchers. One of the most important networks on chip for parallel systems is the multistage interconnection network. In this paper, we propose a design methodology of multistage interconnection networks for massively parallel systems on chip. The framework covers the design step from algorithm level to RTL. We first develop a functional formalization of MIN-based on-chip network at a high level of abstraction. The specification and the validation of the model have been defined in the logic of ACL2 proving system. The main objective in this step is to provide a formal description of the network that integrates architectural parameters which have a huge impact on design costs. After validating the functional model, step 2 consists in the design and the implementation of the Delta multistage networks on chip dedicated to parallel multi-cores architectures on reconfigurable platforms FPGA. In the last step, we propose an evaluation methodology based on performance and cost metrics to evaluate different topologies of dynamic network through data parallel applications with different number of cores. We also show in the proposed framework that multistage interconnection networks are cost-effective high performance networks for parallel SOCs.Request access from your librarian to read this chapter's full text.