Source synchronization and timing Vernier techniques for 1.2 GB/s SLDRAM interface
Y. Morooka, Y. Nakase, Jae-Myoung Choi, Hyunseo Shin, D.J. Perlman, D.J. Kolor, T. Yoshimura, N. Watanabe, Y. Matsuda, Masaki Kumanoya, M. Yamada · 2002
SLDRAM architecture is a proposed standard for high bandwidth, high-speed packetized DRAM. Its I/O interface, SLDRAM interface, is specified for high-speed command/address and data transfers between an SLDRAM controller and SLDRAMs. The SLDRAM interface is demonstrated through a setup involving an experimental chip and an emulation motherboard mounting several SLDRAM emulation modules. The experimental chip is packaged and mounted on a conventional PCB module. The interface of the chip operates up to 600 Mb/s per pin with a 300 MHz clock.