An efficient design of non-linear CA based PRPG for VLSI circuit testing
Sukanta Kumar Das, Debdas Dey, Subhayan Sen, B.K. Sikdar, P.P. Chaudhuri · ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753) · 2004
We report the efficient design of pseudo-random pattern generator (PRPG) with linear time complexity. The PRPG is developed around the regular structure of nonlinear cellular automata (CA). The application of proposed PRPG is demonstrated in designing on-chip test pattern generator (TPG) for VLSI circuits. The quality of the TPG is as good as that designed with the existing schemes, employing maximal length linear CA incurring O(n3) complexity.