Effective TLB thrashing
Andrés R. Hernández C., Wei-Ming Lin · Proceedings of the 37th ACM/SIGAPP Symposium on Applied Computing · 2022
The Memory Management Unit (MMU) in modern processors now includes a Translation Lookaside Buffer (TLB) that caches recently-used Page-Table Entries (PTEs), and prevents carrying out redundant page-table walks during the address translation process. Here, the amount of memory that the TLB can readily translate is commonly known as its reach. Yet, the TLB size, and thus its reach, is limited because the TLB must render a low operation latency due to its place on the critical path to access the cache memory.