A Parallel Circuit Design of Chien Search and Forney Algorithm
Jingxuan Tan, Liguo Zhang, Xingjin Li, Yingzhao Hui, Jiahui Ma, Shengfei Bai · 2021 16th International Conference on Intelligent Systems and Knowledge Engineering (ISKE) · 2021
As an error correction algorithm, Chien search and Forney algorithm are widely used in channel coding. At present, this algorithm mainly has the problem that the search and calculation error time and the hardware resource cost cannot be satisfied at the same time. In order to reduce the consumption of circuit resources while processing data at high speed, this paper proposes a parallel Chien search and Forney algorithm circuit structure, and designs a pipelined Galois field multiplier, uses multiplication factors to simplify Galois field multiplication. Which greatly improves the processing speed of the algorithm. This design is comprehensively verified on the Intel Stratix 10 (1SD280PT2F55E1VG) chip. The results show that the highest clock frequency can reach 402.375MHz and the use of resources is 5%.