Design of an Efficient 4-Bit Serial Parallel Multiplier using QCA
Mary Swarna Latha Gade, S. Rooban · 2021 3rd International Conference on Advances in Computing, Communication Control and Networking (ICAC3N) · 2021
This report provides an effective multi-layer serial-parallel 4-bit multiplier (SPM) using QCA technology. Using a completely used majority gate (MV) and a revised compact and flexible exclusive-OR (C-XOR) gate, we built a bit-serial full adder (BSA). The suggested C-XOR gate has been realized using the QCA cell's properties. For 4-bit multiplier, this updated circuit corresponds to a 38 percent and 26 percent reduction in number of QCA cells and occupied area analogized to the previous design. With QCADesigner, all the proposed layouts were simulated and tested.