A Reproducing-free Chip Power Supply Fault Monitoring Circuit Design
Xingyi Yin, Luo Min, Jianjun Chen, Yaohua Wang, Xiao Hu, Yongwen Wang · 2021 2nd International Conference on Electronics, Communications and Information Technology (CECIT) · 2021
With the rapid improvement of chip integration, chip power supply failure has become a very critical source of chip failure. Existing fault detection methods mainly rely on the measurement of related electrical characteristic parameters after chip faults are reproduced for fault location. However, as power supply faults are hard to be reproduced, it is difficult to locate power supply faults through existing fault detection methods. In order to solve the above problems, this paper proposes a reproducing-free chip power supply fault monitoring circuit design that can monitor the external power supply signal of the chip without failure reproduction. Our design includes a comparator-based glitch and clock monitoring circuit and a time-to-digital conversion(TDC) circuit that calculates the glitch and reset time. The post-imitation test of the design shows that the circuit can support clock frequency in the range of 50MHz to 500MHz, and the accuracy of the measurable clock jitter accuracy is 5% *clock period (UI); it can measure glitches with a minimum of 20mV and a shortest duration of 0.5*UI, and fault with a reset time less than 4 *UI. This can successfully monitor most of the power supply fault. On the basis of post-imitation, we also tape out our design our design in real chip.