Hardware acceleration scheme of Compressed Position Report based on FPGA
Jiaming Chen, Li Li, Sheng Tao, Yao Chen, Haoxi Yang, Qifan Su · 2021 2nd International Conference on Electronics, Communications and Information Technology (CECIT) · 2021
To solve the problems of poor real-time performance and high cost of complex test equipment structure of the existing implementation scheme of CPR coding in 1090ES data chain, an FPGA-based implementation method of CPR coding is proposed. The accelerated coding RTL circuit for single-precision floating-point data is designed using Verilog HDL, simulated by Altera-Modelsim, and compared with the traditional coding method to prove the advantages of the method in terms of computing speed and accuracy. The method is of great significance in improving coding efficiency, reducing device cost, and reducing size, and laying the foundation for specialized ASIC chip design.