Design of 32x32 Reversible Unsigned Multiplier Using Dadda Tree Algorithm
Veena Durgam, K. Ragini · ECS Transactions · 2022
Multipliers are essential parts of every processor or computer. Microcontrollers and digital signal processors typically measure their performance on how many multiplications they can execute in a given amount of time. As a result, better multiplier designs are sure to increase system efficiency. A reversible Dadda multiplier is one such possible approach. The Dadda tree technique is used to construct two 32x32 reversible unsigned multipliers in this paper. The TG and FG gates are accustomed to create the partial product circuit in the first design. The PG and TG are utilized to create a partial product circuit in the second design. For adding partial products, the PG and reversible full adder gates are used. The design is implemented using Xilinx ISE 14.7 design suite.