Design and Synthesis of a 256-Point Radix-2 DIT FFT Core with Design Ware Library using Fixed-Point Number Representation
Deekshith Krishnegowda, Pallavi Nagaraju · 2022 IEEE Delhi Section Conference (DELCON) · 2022
In digital image processing, a time-domain image is converted to the frequency domain to carry out operations such as image enhancing or noise reduction. Discrete time domain image is converted to the frequency domain using Discrete Fourier Transform (DFT) and this lies at the heart of any image processing algorithm. Apart from image processing, Fourier Transform is used in a wide variety of applications from simple radio broadcasting to complication object recognition for autonomous driving purposes. To reduce the computation time of DFT, Fast Fourier Transform (FFT) algorithm was proposed by James W. Cooley and John W. Tukey in 1965. This involved breaking down the DFT of N-length sequence into smaller DFTs of N/2-length with even and odd index terms. DFT can further be broken into real and imaginary parts and accurate representation of this is done through fixed-point number representation in hardware. A fixed-point number consists of a decimal part and a fraction part and arithmetic operations around this type of number representation often require pipelined logic structure to increase throughput. So, in this paper, the implementation of a 256-point DIT (Decimation in Time) FFT algorithm with fixed-point number representation in Verilog is discussed. Pipelined Synopsys Design Ware multiplier IP is used to perform complex FFT multiplication operation. Simulation is performed with Synopsys VCS and waveforms are analyzed with Synopsys Verdi. Synthesis is performed using Synopsys DC (Design Compiler) using Toshiba 45nm library with a target operating frequency of 300Mhz.