Design and Implementation of AXI4-lite Interface in Zynq SoC
Raghuveer Chandaluri, UshaRani Nelakuditi · 2022 IEEE Delhi Section Conference (DELCON) · 2022
Now a days SoC plays a vital role in both academia and industry. In Zynq SoC all devices communicate with one another using the AXI device interface. The Xilinx AXI IP core, which features an AXI4-Lite interface for configuration and control and an AXI4-Stream interface for data transport. This article provides the how to design a new IP (Intellectual Property) for data transfer between PS and PL by using AXI-4 lite in Zynq SoC.