Design of 64-bit Signed Magnitude Comparator using FPGA for IoT applications
B. Jeevan, K. Sivani · 2022 International Conference on Advances in Computing, Communication and Applied Informatics (ACCAI) · 2022
The paper proposes a Novel High Speed a 64-bit Signed Magnitude Comparator (SMC) using Verilog HDL for applications like sorting techniques, digital communication devices, data convertors and address decoding unit of processors. Primarily the Most Significant Bit (MSB) of two 64-bit signed numbers are compared which are represented in 2's complement form and then remaining bits are compared to conclude whether the given numbers are Equal/Greater or lesser than the other. The Leaf Cell of proposed design is 8-bit signed comparator and is extended to 16-bit, 32-bit and finally 64-bit using structural modeling of Verilog HDL. The total delay associated with 64-bit SMC is 8.239ns. The proposed design is functionally verified, synthesized and implemented in the Xilinx Vivado 2012.3 and targeted to Artix-7 FPGA (XC7A100TCSG324C-3). The results of Signed Magnitude Comparator are analyzed in terms of delay, power and area.