Design and Implementation of 2 Bit Ternary ALU Slice
B. S. Saathvik, K.B. Ramesh · Zenodo (CERN European Organization for Nuclear Research) · 2022
This paper describes the architecture, design & implementation of two bit ternary ALU (T-ALU) slice. The proposed ALU is designed for two-bit operation & can be used for n bit operations by cascading n/2 ALU slices. This ALU is implemented the usage of C-MOS ternary logic gates (T-Gates) for ternary mathematics & good judgment circuits. Ternary gates are implemented the use of enhancement / depletion MOSFET generation, consequently proposed ALU is appropriate for LSI / VLSI implementation. The designed approach used right here calls for best levels i.e. decoder & T-gates, as towards three ranges i.e. decoder, binary gates & encoder require in traditional ternary common sense Implementation.