A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2×2 Dielet with 10μm-Pitch Inter-Dielet I/O for Runtime Multi-Program Reconfiguration
Uneeb Rathore, Sumeet Singh Nagi, Subramanian S. Iyer, Dejan M. Markovic · 2022 IEEE International Solid- State Circuits Conference (ISSCC) · 2022
The increasing amount of dark silicon area in power-limited SoCs makes it attractive to consider reconfigurable architectures that could intelligently repurpose dark silicon. FPGAs are more efficient than CPUs, but lack temporal dynamics of CPUs, efficiency and throughput of accelerators. Coarse-grain reconfigurable arrays (CGRAs) can achieve higher throughput, with substantial energy efficiency gap relative to accelerators, and limited multi-program dynamics. This paper introduces a domain-specific and energy-efficient (within 2-10× of accelerators) multi-program runtime-reconfigurable 784-core processor array in 16nm CMOS. Our design maximizes generality for signal processing and linear algebra with minimal area and energy penalty. The main innovation is a statistics-driven multi-layer network which minimizes network delays, and a switch box that maximizes connectivity per hardware cost. The layered network is O(N) with the number of processing elements N, which allows monolithic or multi-dielet scaling. The network features deterministic routing and timing for fast program compile and hardware-resource reallocation, suitable for data-driven attentive processing, including program trace uncertainties and application dynamics. Further, this work demonstrates multiple functional dielets that have been integrated at 10μm bump pitch to build a monolithic-like scalable design. The multi-dielet (2×2) scaling is enabled by energy-efficient high-bandwidth inter-dielet communication channels that seamlessly extend the intra-die routing network across dielet boundaries, quadrupling the number of computeresources.