A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface
Jong Hak Yuh, Jason Li, Heguang Li, Yoshihiro Oyama, Hsu Cynthia, Pradeep Anantula, Stanley Jeong, Anirudh Amarnath, Siddhesh Darne, Sneha Bhatia, Tianyu Tang, Aditya Arya, Naman Rastogi, Naoki Ookuma, Hiroyuki Mizukoshi, Alex Yap, Demin Wang, Steve S. Kim, Yonggang Wu, Min Peng · 2022 IEEE International Solid- State Circuits Conference (ISSCC) · 2022
The presented 1Tb 4b/cell 162 WL layer 3D Flash memory achieves an areal density of 15 Gb/mm2which is 8.7% higher than prior work [1]. High-performance is the key enabler for 4b/cell NAND Flash to enter mainstream systems. This work delivers a 60MB/s programming throughput and a 65μs tRwith an 8kB central WL stair architecture and contact-through-WL (CTW) region. 2.4Gb/s I/O speed is achieved with LTT and CTT combo drivers. A 45% reduction in the read and write data transfer energy is achieved by employing VCCQdomain design. A time-division peak-power-management (TD-PPM) feature effectively reduces system peak power while maximizing system performance. Cache DFT and I/O DFT functions enable a high-speed testing methodology at wafer level. These features are summarized and compared to previously reported 4b/cell Flash memories in Fig. 7.1.1.