An Efficient Design of Scalable Reversible Multiplier with Testability
Hari Mohan Gaur, Ashutosh Kumar Singh, Umesh Ghanekar · Journal of Circuits Systems and Computers · 2022
A new architecture of 4-bit reversible multiplier with scalability factor of order [Formula: see text] is presented in this paper. The design procedure is based on a unique method of gates placement, which produces parity preserving circuits. This property facilitates graceful testing and full coverage of single-bit faults at lower overhead. The circuit is designed and implemented on the top of reversible analyser for obtaining operating costs in terms of number of wires, gate cost, quantum cost, garbage output and ancilla input. Testable implementation of recently reported multiplier circuits has also been performed using the existing method of testing under the same platform. This work achieved a reduction of up to 33% in operating costs when all the parameters are combined together.