A Parallel and Pipelined Hardware Architecture for Fractional-Pixel Motion Estimation in AVS3
Yuning Zeng, Xizhong Zhu, Guoqing Xiang, Zhijian Hao, Peng Zhang, Xiaofeng Huang, Wei Yan · 2022
The latest generation of video coding standards has significantly improved video coding performance. The third generation of audio video coding standards (AVS3) is one of these latest standards. However, due to the more flexible block partition mechanism in AVS3, the computational overhead brought by fractional-pixel motion estimation (FME) increases significantly, making it more difficult to implement a real-time FME hardware. In this paper, a parallel and pipelined hardware architecture supporting block sizes from 4x4 to 64x64 is proposed for FME in AVS3, and it is specially designed for coding tree unit (CTU)-level pipelined architecture of AVS3 encoder. Three necessary modules are developed in this architecture. The first module concerns derivation of motion vector predictors (MVPs). The second module is used to derive fractional-pixel motion vectors (FMVs) of coding units (CUs) partitioned by Binary-tree (BT) and Quad-Tree (QT) mechanisms. And a motion vector substitution (MVS) module is proposed to substitute the FMVs of the remaining CUs with the FMVs derived in the second module. Experimental results show that the proposed methods suffer only 0.62% performance degradation in BD-Rate. Furthermore, the architecture is implemented on XILINX ALVEO U250 FPGA at 400 MHz and the presented FME hardware design can support the real-time encoding of 4K@30fps.