Dynamic Random Access Memory (DRAM)
Shimeng Yu · 2022
1-transistor-1-capacitor (1T1C) DRAM is a mainstream technology that is primarily used as the main memory. This chapter surveys a variety of DRAM’s interface protocols including the DDR, LPDDR, and GDDR series, which aim to prefetch and burst the data to the data bus, thereby increasing the I/O bandwidth. The principle of 1T1C DRAM bit cell operations is introduced, with a focus on the charge-sharing mechanism for sensing. The leakage mechanism in the 1T1C cell is discussed and the DRAM’s periodic refresh operation is illustrated. DRAM’s technology options with the trench capacitor and the stacked capacitor, as well as array architectures with the folded bit line and the open bit line, are presented. The representative 6 F 2 layout rule for the 1T1C cell is shown. DRAM’s scaling challenges and technological innovations are discussed on the cell capacitor, the cell transistor, and the interconnect parasitics, respectively. The recent trend of 3D stacked DRAM with TSV technology is discussed, together with the HBM interface protocol. Lastly, the embedded DRAM is introduced with 1T1C or capacitor-less bit cell, which aims to be logic process compatible.