A Methodology for Evaluating Delay and Power on Binary Counters and Block Level Optimization
Yalla Taraka Venkata Ramana, Bighneswar Panda, B Jeevana Rao, Bhaskara Rao Doddi · International Journal for Research in Applied Science and Engineering Technology · 2022
Abstract: In this paper, slice level optimization is performed on the conventional 6:3 counter and then finally integrated all the slices to the original one. Slice level optimization corresponds to partition the given circuit in to number of blocks such that final integration can be done effectively. Considering individual blocks Power testing and delay testing, results were taken by triggering the activities which lead to power consumption and all possible critical paths were also tested for every individual block and then comparison is made. Test vectors are also applied such that every consecutive cycle output is complemented, so that low to high and high to low delays can be captured with in a smaller number of test vectors. Identical strategy is applied to measure the power because for every two cycles only one power consuming event occurs on a single node under consideration. The proposed 6:3 counter is 36% faster than the conventional one and also saves the power for about 56%. Utilizing more NAND, NOR and AOI gates instead of AND, OR gates have led to the achieved optimization. Keywords: Counter, Delay Testing, Power Testing, Slice level Optimization, Test Vectors