Design of an Interface Test Adapter for Sequential Testing of Transient Voltage Suppressor Diodes to Reduce Test Cycle Time
Francis A. Malabanan, Patricia Angela R. Abu, Carlos M. Oppus, Rosula S. J. Reyes · 2022
The advancement in semiconductor circuit design, particularly its miniaturization has increased the circuit sensitivity to electrical stresses. To protect the circuits, transient voltage suppressor (TVS) diodes are used. This device must be tested with the use of a high-power tester that can surge high inrush power. In a test manufacturing company that employs manual testing of TVS diodes, the cycle time (CT) increases which results in a decrease in the number of units per hour (UPH). The UPH can be increased if the cycle time of the process and human intervention is reduced. In this study, the Design for Six Sigma (DFSS) is used in the design methodology to develop an interface test adapter (ITA) to increase the UPH tested. It is a process flow that guides the research in the creation of ITA. The ITA is interfaced between the current test machine and the unit under test (UUT). It consists of a fixture that holds the UUT and an FPGA board that controls the process. The ITA automates the current fixture by sequentially testing each of the eight bidirectional TVS diodes devices in a single unit vertical array package to reduce the test cycle time. It also minimizes human intervention that avoids human handling error and inconsistency in the process cycle time. Results show that the cycle time per unit has decreased by 20.57%. In terms of UPH tested, this is equivalent to a 48.80% improvement.