High-Speed Speculative Decimal Adder Based on Majority Logic
Tao Wang, Xiaoping Cui · 2022 IEEE 2nd International Conference on Power, Electronics and Computer Applications (ICPECA) · 2022
Due to the demand of high accuracy computation in commercial computing, financial analysis, and other applications, there is a rising demand for high-performance decimal arithmetic. The current decimal adder based on the characteristics of majority logic (ML) is designed by ripple-carry decimal adder (RCDA) with the slower speed. A high-speed speculative decimal adder based on ML is proposed in this paper. The proposed adders are based on an improved design of the binary parallel-prefix network. Compared with the best existing designs, the proposed 64-digit decimal adder achieve over 66% less delay, and has a 39.4% improvement of area-delay product.