A Proposal for Low Power Test Pattern Generator
Maddala Vamsi Krishna, Duppala Tagore, Mani Srikara Yaswanth Nandigam, Palla Narasimha, Udayagiri Rahul, R S Geethu · 2022 4th International Conference on Smart Systems and Inventive Technology (ICSSIT) · 2022
VLSI circuits entitle various challenges in terms of latency, area overhead, and power. Testing a complex circuit of VLSI design, Low power test pattern generation is a critical technique to implement. To minimize the concerned power, a method is proposed at testing mode itself in the very beginning of the circuit working also known as Built-in-self-test (BIST). The paper discusses a Low power test pattern generator (TPG) that works on modified clocks. Polynomials ranging from degree 2 to 11 are implemented for the proposed design using Vivado Tool and the parameters for each polynomial are analyzed from the results obtained. A detailed comparison of the analysis done for the Conventional LFSR and Conventional LFSR with Modified Clock was done.