The iCORE™ 520MHz Synthesizable CPU Core
Nick Richardson, Lun Huang, Razak Hossain, Julian Lewis, Tommy Zounes, Naresh Soni · Kluwer Academic Publishers eBooks · 2005
This chapter describes a new implementation of the ST20-C2 CPU architecture. The design involves an eight-stage pipeline with hardware support to execute up to three instructions in a cycle. Branch prediction is based on a 2-bit predictor scheme with a 1024-entry Branch History Table and a 64 entry Branch Target Buffer and a 4-entry Return Stack. The implementation of all blocks in the processor was based on synthesized logic generation and automatic place and route. The full design of the CPU from micro-architectural investigations to silicon testing required approximately 8-man years. The CPU core, without the caches, has an area of approximately 1.8mm2 in a 6-metal 0.18um CMOS process. The design operates up to 520MHz at 1.8V, among the highest reported speeds for a synthesized CPU core [2].