Development of High Performance Hardware by High-Level Synthesis of Median-Based Dynamic Background Subtraction Method with Multiple Line Buffers
Kohei Shinyamada, Akira Yamawaki · TENCON 2021 - 2021 IEEE Region 10 Conference (TENCON) · 2021
Hardware processing is suitable for embedded image processing systems because of its lower power consumption and higher performance compared to software processing. To facilitate development, a tool called high-level synthesis, which automatically converts high-level languages into hardware description languages, is used. However, high-level synthesis of pure software does not necessarily generate efficient hardware. In this study, we attempted to generate high-performance image processing hardware using a median-based dynamic background subtraction method. As a result, we found that high-performance hardware can be generated when multiple line buffers are introduced. Compared to the non-introduced one, the performance was improved by about 13 times.