CacheGuard: A Behavior Model Checker for Cache Timing Side-Channel Security: (Invited Paper)
Zihan Xu, Lingfeng Yin, Yongqiang Lyu, Haixia Wang, Gang Qu, Dongsheng Wang · 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) · 2022
Defending cache timing side-channels has become a major concern in modern secure processor designs. However, a formal method that can completely check if a given cache design can defend against timing side-channel attacks is still absent. This study presents CacheGuard, a behavior model checker for cache timing side-channel security. Compared to current state-of-the-art prose rule-based security analysis methods, CacheGuard covers the whole state space for a given cache design to discover unknown side-channel attacks. Checking results on standard cache and state-of-the-art secure cache designs discovers 5 new attack strategies, and potentially makes it possible to develop a timing side channel-safe cache with the aid of CacheGuard.